Detailed Study on a Robust and Efficient Fault-Resilient Rad Hard ADPLL

Typically, classical PLLs adopt analog design methods. However integrating PLL with noise-prone application environment is highly tedious and somewhere confined. As per current knowledge majority of PLLs apply Analog Loop Filters (ALFs) and Voltage Controlled Oscillators which are practically highly complicated to integrate with noisy environment. Even the traditional PLLs can’t be ported to the advanced processors. In last few years, the emergence of deep-submicron CMOS technologies have enabled digitization of major traditional analog circuits, comprising the analog PLLs that as a result could be vital to overcome above mentioned issues and to achieve more efficient solution than classical analog implementation. The proposed ADPLL model uses a FDLC based architecture. This architecture model outperforms classical FD-ADPLL model in terms of computational time, power consumption and cost.